While a microprocessor is working, it may be necessary to interrupt the program it is running to execute certain instructions. This is done by using flag signals called interrupts or interrupt requests. An interrupt controller receives these flag signals from peripherals and, depending on the received interrupt, sends to the processor an interrupt command and an interrupt pointer vector. The pointer vector specifies a memory location at which a relative interrupt service routine (ISR) to be run is stored.
The microprocessor then suspends the operation in progress, saves the state of the program being run so that it may resume the program later, and carries out the instructions of the ISR routine relative to the received interrupt. When the ISR routine has been performed, the processor restores the state of the program and, if no other interrupt is pending, resumes the program from the point at which it was interrupted.
Interrupt controllers typically have priority registers for establishing which interrupt, among a plurality of received interrupts that are pending, are to be served first. A basic prior art interrupt control circuit or controller with priority ratings is illustrated in FIG. 1. The interrupt flags, INTO, . . . , INTk, which are generated by peripherals, are stored in a pending interrupt register INT PENDING REG.
The block IRQ MASK AND PRIORITY LOGIC includes a so-called mask of interrupts and a priority logic circuit. The priority logic circuit generates an interrupt request signal IRQ REQ and stores its relative priority HIGHEST PRIORITY INT in the register CURR IRQ PRIORITY REG.
A circuit HIGHEST PRIORITY INT (illustrated with a dashed box) is for processing interrupt request signals based upon the priority thereof. Its core is a state machine IRQ SM which receives as an input an interrupt request signal, and it generates an interrupt command nIRQ for the microprocessor. The interrupt request signal IRQ REQ selects an interrupt vector IRQ VECTOR corresponding to the interrupt to be served, which is read from an interrupt table IRQ VECTOR REG that stores interrupt vectors identifying corresponding ISR routines.
The register CURR IRQ PRIORITY REG and the register INT PRIORITY STACK allow so-called nested interrupts. The register CURR IRQ PRIORITY REG stores the priority of the currently served interrupt. If an interrupt with a higher priority rating is generated, servicing of the first interrupt is suspended and the relative priority is stored in the register INT PRIORITY STACK, while the new interrupt of higher priority is served and its priority is stored in the register CURR IRQ PRIORITY REG.
Once the second interrupt of higher priority has been served, the previously suspended interrupt is resumed, if it has a higher priority than any other pending interrupts. Once it has been served, it is deleted from the stack INT PRIORITY STACK by a command STACK PUSH/POP of the state machine IRQ SM.
The interrupt control circuit has a limited number of input pins dedicated for receiving interrupts from peripherals. Therefore, as illustrated in FIG. 2, only a few peripherals can avail themselves of the dedicated input pins of the interrupt control circuit, while other peripherals share a common input pin for all their interrupts.
As shown in FIG. 3, the peripheral A is connected to the interrupt control circuit INTERRUPT CONTROLLER such that each possible interrupt signal corresponds to a dedicated pin of the control circuit. By contrast, the peripheral B may use only one pin of the interrupt control circuit INTERRUPT CONTROLLER for all of its interrupts.
For peripheral B, the interrupt control circuit receives an interrupt signal IRQm that is obtained by ORing the interrupts stored in the interrupt pending register of the peripheral. When the signal IRQm is active, the interrupt control circuit sends to the microprocessor an interrupt command nIRQ and an interrupt vector IRQ VECTOR identifying a specific interrupt service routine ISR. This results in the reading of the interrupt pending register of the peripheral B for identifying the requested interrupt, and the eventual serving thereof. Of course, this burdens the processor in executing the ISR routine because it has to read the interrupt pending register of the peripheral B before serving the interrupt.